In general, semiconductor materials may be processed in semiconductor technology on or in a substrate (also referred to as a wafer or a carrier), e.g. to fabricate integrated circuits (also referred to as chips). During processing of the semiconductor material, certain processes may be applied, such as forming one or more layers over the substrate, structuring the one or more layers, or contacting the readily fabricated chips.
Conventionally, the sheet resistance of the chip may be reduced by reducing a thickness of the semiconductor material (e.g. silicon). By way of example, for a junction field effect transistor (SFET) a reduction of the thickness of the semiconductor material from 40 μm to 20 μm may result in a decrease of the thickness of the sheet resistance by about 50%. However, reducing the thickness of the semiconductor material increases the vulnerability of the chip to cracking or bending during following processing steps.
To increase the fracture strength of a chip, e.g. for backend processing, a chip-taiko-rim is used, which stabilizes the chip by a thicker rim of the chip made of semiconductor material proximate the kerf and outside the active area of the chip. The active chip area may be selectively thinned to a predetermined thickness. The resulting cavity in the active chip area is filled by a backside metallization, e.g. by electroplating copper, which is time and cost intensive. Furthermore, the copper and the semiconductor material have different thermal expansion coefficients inducing thermomechanical load into the chip, which may increase a failure risk of the readily processed chips. Alternatively, a solder material is used to fill the cavity. The solder material may reduce the manufacturing effort at costs of an increased electrical resistance (more than 12 μOhm·cm in comparison to 1.8 μOhm·cm for copper) and an increased thermal resistance as well as reduced thermal capacity in comparison to copper.